| 摘要 |
PROBLEM TO BE SOLVED: To provide a data input circuit for a synchronous semiconductor memory device. SOLUTION: It is discriminated whether a phase of a data strobe signal leads to a phase of a clock signal or lags by a detecting means, when a phase of the data strobe signal leads more than a phase of the clock signal, the data strobe signal is lagged by one hour, when a phase of the data strobe signal lags more than a phase of the clock signal, the data strobe signal is lagged by two hour. And a first input data signal fetched previously by the data strobe signal in accordance with an output signal of the delay means synchronized with the clock signal. That is this data input circuit synchronizes effectively an internal data signal utilizing internal delay being adjustable when a frequency of the clock signal exceeds the prescribed critical value.
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