发明名称 |
CACHE BUFFER CONTROL METHOD AND CONTROLLER |
摘要 |
PROBLEM TO BE SOLVED: To provide improved cache buffer control for a storage device having a nonvolatile memory medium. SOLUTION: A memory cell of a cache buffer is logically divided into many pages. If a plurality (usually all) of memory cells in a page can store new data, an open condition is registered in a counter in the page. If a memory cell in a page cannot store new data, a full condition is registered in a counter in the page. New data is stored in the page which is registered as the open condition in its counter. The page is weighted based on a reading command rate to give order of priority for the purpose of reading and writing.
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申请公布号 |
JP2003150447(A) |
申请公布日期 |
2003.05.23 |
申请号 |
JP20020219713 |
申请日期 |
2002.07.29 |
申请人 |
FUJITSU LTD |
发明人 |
YONEYAMA KOJI;HIRAO YUICHI;HATAKEYAMA SHIGERU;OLBRICH AARON;PRINS DOUGLAS |
分类号 |
G06F12/12;G06F3/06;G06F12/00;G06F12/02;G06F12/08;G11B20/10;(IPC1-7):G06F12/12 |
主分类号 |
G06F12/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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