发明名称 TEST BENCH FOR LOGIC VERIFICATION
摘要 PROBLEM TO BE SOLVED: To more efficiently and easily verify a design of a large-scale ASIC. SOLUTION: The test bench for verification capable of easily switching an actual circuit to a dummy circuit for respective function modules on the ASIC is fabricated. Thus, at the time of verifying a certain module, by turning the other modules to the dummy circuits and verifying it, generation of an event at the time of a simulation is suppressed and the simulation is accelerated. Also, since only one test bench is prepared and it is not required to prepare the test benches for checking the respective modules, the test bench is easily maintained and managed.
申请公布号 JP2003150662(A) 申请公布日期 2003.05.23
申请号 JP20010351709 申请日期 2001.11.16
申请人 CANON INC 发明人 YUASA NOBUYUKI
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
代理机构 代理人
主权项
地址