HIGH ORDER SYNTHESIS METHOD AND HIGH ORDER SYNTHESIZER

摘要

PROBLEM TO BE SOLVED: To lower power consumption. SOLUTION: An operation description is converted to CDFG (ST11) and scheduling is performed so as to attain a desired number of clock cycles and to minimize a number of registers (ST12). Hardware is allocated to a scheduling result (ST13) and a minimum clock cycle (quasi-synchronous minimum clock cycle) in the case of adjusting a clock timing to the register is obtained (ST14). In the case that the quasi-synchronous minimum clock cycle is larger than the desired clock cycle, after resetting all the clock timings to the same value, a register position inside the CDFG is changed for the purpose of reducing the clock cycle (ST16). In the case that a performance improved by a re-timing processing, a step ST14 is returned. In the case that the performance can not be improved, a processing is ended.