| 摘要 |
PURPOSE: A circuit for controlling a data download of an FPGA(Field Programmable Gate Array) board is provided to design FPGA boards which download data at different speeds simply without an additional circuit or program. CONSTITUTION: When a power is turned on, a power input unit(310) automatically generates a reset signal. A download signal generating unit(320) receives the reset signal from the power input unit(310) and generates a download start signal of an FPGA. An FPGA1(330) receives the download start signal of the download signal generating unit(320) and downloads data of a program module PROM1(340). An FPGA2(350) receives a download completion signal of the FPGA1(330) and downloads data of a program module PROM2(360). Although a data download speed from the program module PROM1(340) by the FPGA1(330) is different from a data download speed from the program module PROM2(360) by the FPGA2(350), the other FPGA is not decided as an inferiority by an FPGA which completed a download.
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