发明名称 CAPACITANCE EXTRACTION METHOD AT THE TIME OF DESIGNING LAYOUT INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a capacitance extraction method capable of highly accurately extract a capacitance and shortening the time required for the capacitance extraction. SOLUTION: The capacitance extraction method at the time of designing a layout of an integrated circuit is provided with a process of obtaining a first capacitance value when an object cell is present singly, a process of obtaining a second capacitance value that the object cell has when an adjacent cell arranged adjacently to the object cell is present, a process (step S1) of calculating a capacitance difference value which is a difference between the first capacitance value and the second capacitance value and preserving the object cell, the adjacent cell and the capacitance difference value, a process (step S3) of recognizing the adjacent cell adjacent to the object cell in a plurality of the cells arranged according to layout information (step S2) and a process (step S4) of obtaining the capacitance difference value corresponding to the recognized adjacent cell and the object cell from the preserved capacitance difference value an adding the obtained capacitance difference value to the first capacitance value that the object cell has.
申请公布号 JP2003150664(A) 申请公布日期 2003.05.23
申请号 JP20010352015 申请日期 2001.11.16
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 MIYAZONO YUKO
分类号 G01R27/26;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G01R27/26
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