METHOD TO CONTROL THE CHANNEL LENGTH OF A VERTICAL TRANSISTOR BY FIRST FORMING CHANNEL USING SELECTIVE EPI AND SOURCE/DRAIN USING IMPLANTATION,申请号SG20010006790-传众专利搜索

发明名称	METHOD TO CONTROL THE CHANNEL LENGTH OF A VERTICAL TRANSISTOR BY FIRST FORMING CHANNEL USING SELECTIVE EPI AND SOURCE/DRAIN USING IMPLANTATION
摘要
申请公布号	SG96252(A1)	申请公布日期	2003.05.23
申请号	SG20010006790	申请日期	2001.11.05
申请人	CHARTERED SEMICONDUCTOR MANUFACTURING, LTD	发明人	YING KEUNG LEUNG;YELEHANKA RAMACHANDRAMURTHY PRADEEP;JIA ZHEN ZHENG;LAP CHAN;ELGIN QUEK;RAVI SUNDARESAN;YANG PAN;JAMES YONG MENG LEE
分类号	H01L21/336;(IPC1-7):H01L21/332	主分类号	H01L21/336
代理机构		代理人
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