| 摘要 |
An analog delay circuit integrally formable on a semiconductor substrate and providing an improvement in accuracy of delay time. An analog delay circuit 24 includes a clock generating part 50, analog switches 51-56, 61-66, inverter circuits 71-76, and capacitors 81-86, 90. The switches 51-56 are sequentially rendered conductive, thereby causing capacitors 81-86 to hold the voltages of input signals at the respective time points. Before these held voltages are updated, the switches 61-66 are rendered conductive, thereby deriving the held voltages. In this way, the time periods from when the switches 51-56 are rendered conductive to when the respectively associated switches 61-66 are rendered conductive, that is, signal output timings are delayed.
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