A processor assisted memory BIST to identify defective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.
申请公布号
WO0221234(A3)
申请公布日期
2003.05.22
申请号
WO2000SG00132
申请日期
2000.09.06
申请人
INFINEON TECHNOLOGIES AG;PANDEY, PRAMOD, KUMAR;NAJAFI, ALI