发明名称 Interruptible and re-entrant cache clean range instruction
摘要 A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequence of instructions (800) in accordance with a program counter. If an interrupt (804) is received during execution of the clean instruction, execution of the clean instruction is suspended before it is completed. After performing a context switch (810), the interrupt is serviced (820). Upon returning from the interrupt service routine (830, 834), execution of the clean instruction is resumed by comparing the start parameter and the end parameter provided by the clean instruction with a current content of a respective start register and end register used during execution of the clean instruction. If the same, execution of the clean instruction is resumed using the current content of the start register and end register. If different, execution of the clean instruction is restarted by storing the start parameter provided by clean instruction in the start register and by storing the end parameter in the end register. In this manner, no additional context information needs to be saved during a context switch in order to allow the clean instruction to be interruptible. If the interrupt occurred during a non-interruptible instruction, then the instruction is completed before the context switch and a return (830, 832) after the interrupt service routine begins execution at the next instruction (803). Other instructions that perform a sequence of operations can also be made interruptible in a similar manner.
申请公布号 US2003097550(A1) 申请公布日期 2003.05.22
申请号 US20020157576 申请日期 2002.05.29
申请人 CHAUVEL GERARD;LASSERRE SERGE;D'INVERNO DOMINIQUE 发明人 CHAUVEL GERARD;LASSERRE SERGE;D'INVERNO DOMINIQUE
分类号 G06F9/30;G06F9/48;G06F12/08;(IPC1-7):G06F9/00 主分类号 G06F9/30
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