发明名称 |
ERROR CORRECTING MEMORY AND METHOD OF OPERATING SAME |
摘要 |
A memory device that uses error correction code (ECC) circuitry to improve the reliability of the memory device in view of single-bit errors caused by hard failure or soft error. A write buffer is used to post write data, so that ECC generation and memory write array operation can be carried out in parallel. As a result there is no penalty in write latency or memory cycle time due to ECC generation. A write-back buffer is used to post corrected ECC words during read operations, so that write-back of corrected ECC words does not need to take place during the same cycle that data is read. Instead, write-back operations are performed during idle cycles when no external memory access is requested, such that the write back operation does not impose a penalty on memory cycle time or affect memory access latency. |
申请公布号 |
WO03042826(A2) |
申请公布日期 |
2003.05.22 |
申请号 |
WO2002GB05123 |
申请日期 |
2002.11.13 |
申请人 |
MONOLITHIC SYSTEM TECHNOLOGY, INC;FREEMAN, JACQUELINE, CAROL |
发明人 |
LEUNG, WINGYU;HSU, FU-CHIEH |
分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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