发明名称 ALIGNER AND EXPOSURE METHOD
摘要 PROBLEM TO BE SOLVED: To provide an aligner capable of eliminating failure partially caused on a conductor pattern on a printed circuit board due to post-stages. SOLUTION: In this aligner (100) to form a circuit pattern drawn on a mask (20) on a board (10) by using light sources (U1, U2...) including a plurality of light emitting parts respectively radiating light toward the board (10), light quantity data showing a relationship between positions where the respective light emitting parts radiate the light and light quantity to be outputted by the light emitting parts is preserved in a storage means (120) on the basis of post-stage characteristics information showing, for every different area on the board, the characteristics of the circuit pattern on the board to which the post- exposure processing is applied. Then, the light quantity of each of the light emitting parts is controlled on the basis of the light quantity data stored in the storage means.
申请公布号 JP2003149826(A) 申请公布日期 2003.05.21
申请号 JP20010351317 申请日期 2001.11.16
申请人 PENTAX CORP 发明人 ISHIBASHI SHIGETOMO;HARA MASATO;KOBAYASHI YOSHINORI
分类号 G03F7/20;H01L21/027;H05K3/00;(IPC1-7):G03F7/20 主分类号 G03F7/20
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