Merged data line test circuit for classifying and testing a plurality of data lines, and test method performed by the same

摘要

A merged data line test circuit classifies a plurality of data lines for merged and separated testing. In the merged data line test circuit, a control signal generator simultaneously asserts first and second control signals in response to a merged-test signal and alternately asserts the first and second control signals in response to a separated-test signal. A first comparison unit compares the data lines in a first data line group in response to the first control signal. A second comparison unit compares the data lines in a second data line group in response to the control second signal. A driver outputs merged data signals according to the outputs of the first and second comparison units. An external test circuit can examine the output merged data signals to detect a defect and generate the merged-test signal and the separated-test signal in a manner that identifies the location of a defective memory cell. Preferably, the separated-test signal is set so that the first and second signals are alternately activated.