发明名称 |
Pulsed circuit topology to perform a memory array write operation |
摘要 |
A pulsed circuit topology to perform a memory array write operation. A write enable pulse width control circuit is responsive to a pulsed clock signal to generate a pulsed write enable signal and a write data path circuit is provided to output a write data signal. The write enable pulse width control circuit and the write data path circuit together control a write operation to a memory cell.
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申请公布号 |
US6567337(B1) |
申请公布日期 |
2003.05.20 |
申请号 |
US20000607897 |
申请日期 |
2000.06.30 |
申请人 |
INTEL CORPORATION |
发明人 |
SPRAGUE MILO D.;LI DAVID K.;MURRAY ROBERT J. |
分类号 |
G11C7/10;G11C7/22;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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