| 摘要 |
Disclosed is a circuit for controlling output currents of the data ports in a Rambus DRAM having two data ports DQA and DQB. The disclosed circuit arrangements save power and require less chip "real estate' than do known circuit arrangements. First and second current evaluation means output first and second control signals respectively by evaluating currents of the data ports DQA and DQB. A current control value producing means produces a next current control value for the data port DQA by receiving the first control signal and a present current control value of the data port DQA and producing another next current control value for the data port DQB by receiving the second control signal and a present current control value of the data port DQB. The current control value producing means repeats the process to produce the next current control values alternately, and first and second control value latch means for latching the respective current control values of the data ports DQA and DQB produced by the current control value producing means.
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