Semiconductor memory device using dedicated command and address strobe signal and associated method

摘要

Provided is a synchronous DRAM capable of reducing latency corresponding to a time difference between the arrival of commands and addresses and the arrival of a system clock. The synchronous DRAM safely transmits the commands and addresses to all the synchronous DRAMs of a memory module within a clock cycle time even when the frequency of the system clock increases. An associated method is additionally provided. The synchronous DRAM receives a dedicated command and address strobe signal, different than the system clock. The dedicated command and address strobe signal allows safe transmission of the commands and addresses to all synchronous DRAMs of a memory module regardless of the frequency of the system clock.