发明名称 |
Parallel push algorithm detecting constraints to minimize clock skew |
摘要 |
A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.
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申请公布号 |
US6566924(B2) |
申请公布日期 |
2003.05.20 |
申请号 |
US20010911398 |
申请日期 |
2001.07.25 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. |
发明人 |
LIN SHEN;CHANG NORMAN;LEE KEUNMYUNG;NAKAGAWA OSAMU;XIE WEIZE |
分类号 |
G06F1/10;H03L7/00;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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