发明名称 |
Zero phase and frequency restart PLL |
摘要 |
A circuit generally comprising a first circuit and a phase lock loop. The first circuit may be configured to (i) collect a plurality of samples per cycle during a plurality of cycles of an input signal and (ii) calculate a phase offset and a frequency offset for the input signal relative to a clock signal in response to the samples. The phase lock loop may be configured to (i) preset a phase error signal to the phase offset and a frequency error signal to the frequency offset and (ii) generate the clock signal in response to the phase error signal and the frequency error signal.
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申请公布号 |
US6566922(B1) |
申请公布日期 |
2003.05.20 |
申请号 |
US20010052929 |
申请日期 |
2001.10.29 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
SCHELL DAVID L.;WINDLER PETER J. |
分类号 |
G11B20/14;H03L7/091;H03L7/10;(IPC1-7):G11B5/09 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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