Pulse signal delay circuit

摘要

A pulse delay circuit includes a delay circuit, a plurality of selectors and a plurality of synchronous circuits. The delay circuit includes a plurality of series connected delay elements for delaying a clock signal and generating a plurality of delay clock signals. Each of the selectors is connected to the plurality of delay elements and selects one of the plurality of the delay clock signals in accordance with an associated selection signal. The plurality of synchronous circuits receive pulse signals and the selected delay clock signals and generating a plurality of synchronous pulse signals that are synchronized with the selected delay clock signals, respectively.