发明名称 |
Graphoepitaxial conductor cores in integrated circuit interconnects |
摘要 |
A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core with a random grain texture fills the opening over the barrier layer. The crystallographic orientation of the conductor core is then graphoepitaxially changed to reduce its random grain texture.
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申请公布号 |
US6566248(B1) |
申请公布日期 |
2003.05.20 |
申请号 |
US20010759114 |
申请日期 |
2001.01.11 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
WANG PIN-CHIN CONNIE;TRAN MINH QUOC |
分类号 |
H01L21/768;(IPC1-7):H01L21/476;H01L21/44 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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