| 摘要 |
An asynchronous logic circuit allows a host Controller or hub to enter a low power state with its clock suspended. When a power manager calls for a low power state, the clock in the host or hub is suspended and the asynchronous logic circuit is engaged. The asynchronous logic circuit can detect events on the port while the host or hub is in the low power mode. The asynchronous logic circuit generates a downstream signal if required and sends out a wake up signal to the power manager. After the host or hub is awake, the host or hub regains control of the bus and the asynchronous logic circuit is disengaged.
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