发明名称 DEVICE, METHOD AND PROGRAM FOR SAVING POWER OF LOGIC CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To solve the problem of difficulty in coping with the design of a complex logic circuit resulting from the need to predetermine an internal circuit to be given a low power consumption mode and the need to design while taking into account a plurality of signal values to be inputted to a state monitor circuit 100 in setting the internal circuit at the low power consumption mode. SOLUTION: A device for saving the power of the logic circuit includes a storage means for storing logic design information consisting of information on connections between circuit elements constituting the logic circuit, and a circuit adding means for adding a power saving circuit for which predetermined circuit elements to be operated only when input signal values vary are preset, and which extracts from the logic design information the connection information of the predetermined circuit elements and supplies operation clock signals to the predetermined circuit elements according to the connection information only when the input signal values vary.</p>
申请公布号 JP2003141198(A) 申请公布日期 2003.05.16
申请号 JP20010339844 申请日期 2001.11.05
申请人 MITSUBISHI ELECTRIC CORP 发明人 MOTOYAMA NOBUAKI
分类号 G06F17/50;G06F1/04;(IPC1-7):G06F17/50 主分类号 G06F17/50
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