发明名称 DIGITAL TELEVISION RECEIVER, VIDEO DATA TRANSMISSION CIRCUIT AND VIDEO DATA RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To enable serial data transmission of video data at a low transmission speed of 20 Mbps or less. SOLUTION: A video data output means 10 outputs a video image clock and video image data. If a serial data transmission speed is lower than prescribed, a first select means 14 outputs a video clock multiplied by a clock multiplier circuit 13 to a serial data transmission means 15 by a selection signal of a selection means 11. Also, the video clock is outputted as a reproduction clock from a reproduction clock means 12 by the selection signal of the means 11. The means 15 transmits video data, a reproduction clock, the selection signal, and a synchronous clock to a serial data receiving means 16. The means 16 outputs the video data, the regenerated clock, the selection signal and the synchronous clock from the received serial data. A second select means 17 outputs the regenerated clock by the selection signal, and a video data receiving means 18 receives the video data synchronously with the regenerated clock. In this way, serial data transmission with a low transmission speed can be enabled.
申请公布号 JP2003143499(A) 申请公布日期 2003.05.16
申请号 JP20010335345 申请日期 2001.10.31
申请人 SONY CORP 发明人 WATANABE HIDEKI
分类号 H04N5/44;(IPC1-7):H04N5/44 主分类号 H04N5/44
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