SIMULATION METHOD AND DEBUG METHOD FOR VERIFYING ROUTINE EXECUTING ORDER OF PROCESSOR, DEBUGGER PROGRAM, AND ITS RECORDING MEDIUM

摘要

PROBLEM TO BE SOLVED: To easily and efficiently verify an operation for an external signal of a logically designed processor. SOLUTION: A verified model 21 in which a processor 23, a program RAM 24, a data RAM 25, and a peripheral I/O device 26 are interconnected via a bus, and a test bench 22 for interrupting the processor 23 via the peripheral I/O device 26 are described in a hardware describing language. A test program 14 including a main routine to be processed by the processor 23 and an interrupt handling routine corresponding to each interrupt factor is described in an assembly language. A command of writing an interrupt handling routine identifying code into a trace storing region RV in the data RAM 25 is inserted into each interrupt handling routine. The verified model 21 and the test bench 22 are simulated, and then a trace value RV is compared with an expected value EV to verify the interrupt routine executing order.