Secure identification and receiver-side selection of channels for Synchronous Digital Hierarchy transmitted Synchronous Transfer Mode-1 signals is performed by circuit with shift- and buffer-registers

摘要

A MID-Detection-Module switching circuit (1) includes a circuit (12) which identifies Frame Align Sequence Module identification words and is connected via registers to the core of the receiver (13). It sends a MID-Enable signal (a) and a 78 MHz signal to an AND-gate (9) connected to a MID-Shift-Register (2). There is a Dual Data direct connection to this register. The MID-Shift-Register is connected to a MID-Buffer register (3) and a first comparator (5). There is a further connection to a MID-Code-Register (4) with connections to a second comparator (7) and the core of the receiver. The switching circuit includes plausibility checking circuits (6,8) and a second AND-gate (9').