In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).
申请公布号
WO0248722(A3)
申请公布日期
2003.05.15
申请号
WO2001US47625
申请日期
2001.12.10
申请人
INTEL CORPORATION;ANALOG DEVICES, INC.
发明人
ROTH, CHARLES, P.;SINGH, RAVI, P.;KOLAGOTLA, RAVI;DINH, TIEN