Multiprozessorsystem und Kommunikationsverfahren zwischen Prozessoren

摘要

In a multiprocessor system including a plurality of processors (1A to 1N) and asynchronous transfer mode (ATM) switches (2A to 2M) in the number corresponding to a bit width of internal buses (9) of respective processors (1A to 1N) each processor has an interface (10) for connecting in parallel to each of the plurality of ATM switches (2A to 2M). Each interface (10) splits a transmission data block (34) into a plurality of bit data blocks (35) at every bit position, converts them into a plurality of cells (31) by adding a header (32) including routing information determined by a destination processor to each bit data block, and sends these cells (31) in parallel to the plurality of ATM switches (2A to 2M). The plurality of cells (31) are transferred in parallel to the destination processors by the ATM switches (2A to 2M) and reassembled into an original data block in the interface of the destination processor.