| 摘要 |
It is disclosed a semiconductor memory device and data output buffer thereof in which an area of a layout can be optimized. The semiconductor memory device includes a plurality of memory cell array blocks, a plurality of sense amplifiers arranged above (or below) the plurality of the memory cell array blocks for amplifying and outputting data outputted from each of the plurality of the memory cell array blocks, a plurality of first registers arranged adjacent each of the plurality of the sense amplifiers for storing a pair of sense output signals outputted from each of the plurality of the sense amplifiers and generating a first data output signal, a plurality of second registers arranged respectively below (or above) the plurality of the memory cell array blocks for receiving the first data output signal outputted from each of the plurality of the first registers in response to the clock control signal and an output enable signal and generating a pair of second data output signals, a plurality of output drivers arranged respectively below (or above) the plurality of the memory cell array blocks for driving the second data output signal pair outputted from the plurality of the second registers, and a plurality of input/output pads connected to each of the plurality of the output drivers.
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