发明名称 Multiplier circuit comprising a plurality of multiplier segments
摘要 A multiplier circuit comprises a plurality of multiplier segments each receiving operand words of a first length and input selectors, e.g. input Sel which can be high or low, which select a first set of inputs when the multipliers are to operate individually and a second set such that the multiplier segments are concatenated to form a wider multiplier operating on operands of a second word length. The circuit is used as a secret key multiplier to implement a wider width key in programmable encryption.
申请公布号 GB2381913(A) 申请公布日期 2003.05.14
申请号 GB20030002861 申请日期 1999.02.26
申请人 * MOSAID TECHNOLOGIES INCORPORATED 发明人 DAVID E * JONES;CORMAC M * O'CONNELL
分类号 G06F7/50;G06F7/52;G06F7/72;H04L9/00;H04L9/06;H04L9/30;(IPC1-7):G06F7/52 主分类号 G06F7/50
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