发明名称 Monotonic dynamic static pseudo-NMOS logic circuits
摘要 A method and apparatus for evaluating logical inputs electronically using electronic logic circuits in monotonic dynamic-static pseudo-NMOS configurations. The apparatus includes alternating dynamic and static circuit portions adapted to transition monotonically in response to a common clock (or complemented clock) signal. The circuit portions include pseudo-NMOS configured switching circuits implementing logical functions.
申请公布号 US6563345(B2) 申请公布日期 2003.05.13
申请号 US20010805909 申请日期 2001.03.15
申请人 MICRON TECHNOLOGY, INC. 发明人 FORBES LEONARD
分类号 H03K19/096;(IPC1-7):H03K19/096 主分类号 H03K19/096
代理机构 代理人
主权项
地址