发明名称 |
Method and structure of a dual/wrap-around gate field effect transistor |
摘要 |
Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.
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申请公布号 |
US6563131(B1) |
申请公布日期 |
2003.05.13 |
申请号 |
US20000586501 |
申请日期 |
2000.06.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ADKISSON JAMES W.;AGNELLO PAUL D.;BALLANTINE ARNE W.;PUTNAM CHRISTOPHER S.;RANKIN JED H. |
分类号 |
H01L21/336;H01L29/423;H01L29/78;H01L29/786;(IPC1-7):H01L29/06;H01L29/76;H01L27/12 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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