发明名称 Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
摘要 A portion of an integrated circuit (IC) is operated at a high operating frequency while the IC communicates at a bus frequency during a first period of time. A throttle signal is sent to the IC, and in response, the high operating frequency is reduced to a low operating frequency. The portion of the IC is then operated at the low operating frequency while the IC communicates at the bus frequency during a second period of time. Alternatively, the IC, in response to the throttle signal, stalls at least a portion of a pipeline or issues no-ops to the pipeline.
申请公布号 US6564332(B1) 申请公布日期 2003.05.13
申请号 US19980220991 申请日期 1998.12.23
申请人 INTEL CORPORATION 发明人 NGUYEN HANG T.;KLING RALPH M.;GROCHOWSKI EDWARD T.
分类号 G06F1/32;(IPC1-7):G06F1/30;G06F1/28 主分类号 G06F1/32
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