| 摘要 |
PURPOSE: A turbo decoder is provided to reduce a critical path delay through a simple structure and obtain a high decoding performance. CONSTITUTION: A subtracter(110) subtracts the second input(y) from the first input(x). A code bit output part(120) detects an output value of the subtracter(110) and outputs a code bit as a select signal. A multiplexor(130) selects a relatively large value of the inputs(x,y) in response to an output of the code bit output part(120). An absolute value comparing part(140) determines whether an absolute value of an output of the subtracter is less than '1', and outputs a '1' value when the absolute value is less than or same to '1'. An adder(150) adds an output value of the absolute value comparing part to an output value of the multiplexor and calculates a new path matrix(max'(x,y)).
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