发明名称 INSTRUCTION-EXECUTION METHOD USING MICROPROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a high-performance RISC based super-scalar type processor architecture which fits to be implemented on a microprocessor. SOLUTION: The microprocessor fetches an instruction set from an instruction store in order to be interpreted and executed. The microprocessor is constituted with an instruction set capture means to capture the instruction set designated to be executed in advance including an instruction to refer a register, a data store means to store data on plural registers including the register designated in advance and a transient register, and an execution means which is connected to the instruction set capture means and means to sequentially execute the instruction set designated in advance. The microprocessor directs the data processed by the instruction executed out of a sequence to be stored on the transient register, and is the above register designated in advance which is the register referred by the instruction executed out of the sequence.
申请公布号 JP2003131869(A) 申请公布日期 2003.05.09
申请号 JP20020267998 申请日期 2002.09.13
申请人 SEIKO EPSON CORP 发明人 GUEN RE TORON;LENZ DEREK J;MIYAYAMA YOSHIYUKI;GARGU SANJIBU;HAGIWARA YASUAKI;WANG JOHANNES;LAU TERRY;TORAN KUWAN H
分类号 G06F9/32;G06F9/30;G06F9/34;G06F9/38;G06F9/42;(IPC1-7):G06F9/38 主分类号 G06F9/32
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