发明名称 DEQUANTIZING CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide an inverse quantization circuit adapted to MPEG-4 and the like, which can bring decrease in power consumption and size reduction of a chip mounted on the inverse quantization circuit, by decreasing the number of wiring. SOLUTION: At a double increment unit 5, processing is conducted to determine an OR processed value for a section of the bit 11 and the bit 10 of|QF[i] (AC/DC quantization coefficient)|as the value of the bit 11 of an output A[i], a section from the bit 9 to the bit 0 of|QF[i]|as a section from the bit 10 to the bit 1 of the output A[i], and the bit 0 of the output A[i] as '1'.</p>
申请公布号 JP2003133961(A) 申请公布日期 2003.05.09
申请号 JP20010327061 申请日期 2001.10.25
申请人 FUJITSU LTD 发明人 KOMAZAKI HIROSHI;NAKAYAMA HIROSHI
分类号 H04N19/50;H03M7/14;H03M7/30;H04N19/30;H04N19/42;H04N19/44;H04N19/91;(IPC1-7):H03M7/14;H04N7/32 主分类号 H04N19/50
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