| 摘要 |
<p>PROBLEM TO BE SOLVED: To control the order for shifting/returning to/from the power-saving mode between a CPU and a peripheral equipment. SOLUTION: A register 13141 which is accessible from the CPU via a system bus is provided in the control circuit of the peripheral equipment. After the CPU makes access to the resister 13141, it shits to the power-saving mode, and after a peripheral control circuit receives the access from the CPU, it shifts the peripheral equipment to the power-saving mode by a timer 13145 after a prescribed period of time passes. Similarly, after a prescribed returning signal is inputted, it returns the peripheral equipment to the original state by a timer 13146 after a prescribed period of time passes. In this case, the CPU returns by a delayed signal generated by delaying a return signal 193 by a prescribed time with a delayed circuit. Timer-setting time and so on are set by the CPU in the registers 13142 and 13143 connected to the system bus. The order for shifting/returning is controlled by the magnitude of the time.</p> |
