| 摘要 |
PURPOSE: To provide an input/output circuit equipped with a termination circuit which restrains increase in the chip area. CONSTITUTION: The circuit is provided with an output buffer, an input buffer 10 and a control circuit 20. The output buffer consists of a 1st series circuit comprised of a transistor MP11 and a resistor R11, and a 2nd series circuit comprised of a transistor MP12 and a resistor R13 which are connected in parallel between a high-level side power supply VDDQ and an input/output terminal DQ, a 3rd series circuit comprised of a transistor MN11 and a resistor R12, and a 4th series circuit comprised of a transistor MN12 and a resistor R14 which are connected in parallel between a low-level side power supply GND and the input/output terminal DQ. The input buffer 10 where its input terminal is connected to the input/output terminal DQ. The control circuit 20 which controls at output, common supply of the signal that is obtained by inverting output data to the gates of the transistors MP11, MP12, MN11, and MN12, and at input, applying the VDDQ and the GND power supply voltages respectively to the gates of the transistors MP11 and MN11, and applying the GND and the VDDQ power supply voltages respectively to the control terminals of the transistor MP12 and the MN12.
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