| 摘要 |
PROBLEM TO BE SOLVED: To overcome a problem such that in conventional multiplexer circuits, reducing the resistance value of pullup resistors in order to enable fast operation increases the power consumption and the delay due to a transfer-gate interposed in series with parallel data makes fast operation difficult. SOLUTION: This multiplexer circuit is provided with a plurality of multiplexer cells 100 (10 to 13) where each of the cells converts the parallel data to serial data in synchronization with clock signals CLK0 and CLK1. The circuit has a first load 101 and a plurality of first conductivity type transistors 103 and 104 connected in series between a first line Vdd of power and a second line Vss of power, and a level-shifting means 105 for level-shifting a connection node PN between the adjacent first conductivity type transistors toward the first line of power. |
