| 摘要 |
PROBLEM TO BE SOLVED: To provide the configuration of a PL-TEG pattern, where the size and the position of a defect can be inspected and determined in short time, in the development and manufacture of a semiconductor integrated circuit, and to provide the determining method. SOLUTION: A process level test element group on a substrate is formed by the wiring defect evaluating pattern of the semiconductor circuit having four terminal patterns 11, two conductor patterns 12 and 13 which are connected to the two groups of terminals and are separated by equal intervals and one or above resistance patterns 15 of different resistances in between two conductor patterns. The wiring defect evaluating method of the semiconductor circuit is constituted of a measurement step for measuring the electrical resistance among the four terminals disposed at both ends of the conductors of the patterns, a standard value step for obtaining a standard resistance which is logically obtained from the equivalent circuit of the evaluation pattern by data designing the evaluation pattern and a detection/determination step for comparing the data obtained in the measurement step, with the data calculated in the standard value step and determining the size and the position of the defect. |
