| 摘要 |
PROBLEM TO BE SOLVED: To provide a delay circuit comprising a delay line with multiple delay stages connected in series and an interpolation delay circuit capable of subdividing delay for adjusting delay quantity, in which fixed delay quantity peculiar to the circuit is reduced so that a high frequency operation can be achieved. SOLUTION: A delay circuit 100 is provided with a first delay block 10 and a second delay block 20. The first delay block 10 comprises multiple delay stages A1 through An connected in series, and output from each unit can also be branched off. The second delay block 20 comprises a first driving circuit 21 and a second driving circuit 22, having driving inverters connected in parallel, and varies its output delay by controlling these driving inverters' states as active or non-active, respectively. In this delay circuit 100, in order to realize branch output from the first delay block 10, each output node is provided with a tristate buffer, and output from each tristate buffer is fixedly input to either the first driving circuit 21 or the second driving circuit 22. |
