发明名称 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce the occurrence of short circuitings among wires of the same layer in damascene wiring. SOLUTION: After connection holes 10 are formed in an interlayer insulating film 9 formed on lower-layer wiring 7, the holes 10 are filled up by forming a barrier metal layer and a Cu film over the whole surface of a substrate 1, including the insides of the holes 10. Then plugs 13 are formed by removing the barrier metal layer and Cu film from the surface of the substrate 1, except the holes 10 by the CMP method. Thereafter, the irregular surface of the insulating film 9, caused by the recess 8 of the lower-layer wiring 7 and the recess 14 of the area where the plugs 13 are formed closely to each other, is planarized by preferentially polishing the surface of the insulating film 9 by the CMP method. Consequently, occurrence of short circuitings among wires caused by the left unpolished part of upper-layer wiring formed by the damascene method can be reduced.
申请公布号 JP2003133314(A) 申请公布日期 2003.05.09
申请号 JP20010332126 申请日期 2001.10.30
申请人 HITACHI LTD 发明人 TORII KATSUHIRO;YAMADA YOHEI;KONISHI NOBUHIRO
分类号 H01L21/3205;H01L21/304;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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