METHOD FOR DELAY LOCK AND DLL USING THE SAME

摘要

PURPOSE: A method for delay lock and a DLL(Delay Locked Loop) using the same are provided to reduce an initial lock-on time and the number of used elements by using effectively a successive approximation mode. CONSTITUTION: A mode control signal generation portion generates a mode control signal to indicate the execution of a successive approximation mode for phases of an internal clock signal and a reference clock signal on the basis of a phase relation signal and an external reset signal. A shift register portion(100) outputs plural bits in parallel by shifting unit bits from the most significant bits on the basis of the mode control signal and the external reset signal. A plurality of data format portions(120a to 120f) outputs the successively approximated data bit streams according to the decided increase of corresponding bits. A delay control bit stream output portion(130) stores the data bit streams from the data format portions(120a to 120f) and outputs the stored data bit streams to the delay control bit streams.