| 摘要 |
PURPOSE: An output circuit for reducing a skew is provided to increase an operating speed by reducing a signal delay according to data patterns. CONSTITUTION: A majority voter decision portion(103) is used as a control block for controlling a delay block(105). The majority voter decision portion(103) generates a high level control signal or a low level control signal to the delay block(105) according to the number of input signals. The delay block(105) is formed with eight unit delay blocks. One unit delay block corresponds to one bit of eight data bits. Each unit delay block is formed with two delay portions having different delay time. The delay block(105) receives the data of the register portion(101) according to the high level control signal or the low level control signal and outputs the data to a driver(107).
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