发明名称 STRESS-TESTING CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND STRESS-TESTING METHOD USING THE STRESS-TESTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a stress-testing circuit and a stress-testing method for quickly and easily executing the stress test of a transistor switch in a semiconductor integrated circuit for selecting a multiple-value analog gradation voltage by a plurality of transistor switches for outputting. SOLUTION: In the semiconductor integrated circuit, a breaking means 22 for breaking the supply of a gradation voltage from a gradation voltage supply means 21 to a gradation voltage supply line 47, continuity-controlling means 55 and 56 for simultaneously setting all of transistor switch circuits 45 to a continuity state, and a potential-controlling means 51 for controlling a terminal connected to the gradation voltage supply line 47 of all the transistor switch circuits 45 to grounding potential or power supply potential are provided. PMOS and NMOS transistors for composing the transistor switches 45 are alternately selected, and a stress voltage is applied for specific time, thus executing the stress test of all the transistors in two stress application cycle times.
申请公布号 JP2003130921(A) 申请公布日期 2003.05.08
申请号 JP20010330999 申请日期 2001.10.29
申请人 SHARP CORP 发明人 IGAKI TOSHIAKI
分类号 G01R31/30;G01R31/28;G02F1/13;G02F1/133;G09G3/20;G09G3/36;(IPC1-7):G01R31/30 主分类号 G01R31/30
代理机构 代理人
主权项
地址