发明名称 METHOD AND ARCHITECTURE FOR SELF-CLOCKING DIGITAL DELAY LOCKED LOOP
摘要 An apparatus (100) comprises a delay line (112) and a control circuit (116). The delay line (112) is configured to generate an output signal (132) in response to an input signal (122) and one or more control signals (137, 138). The delay line (112) is self-clocked. A phase of the output signal (132) is adjusted in response to the one or more control signals (137, 138). The control circuit (116) is configured to generate the one or more control signals (137, 138) in response to the input signal (122) and the output signal (132).
申请公布号 WO03039003(A1) 申请公布日期 2003.05.08
申请号 WO2002US34665 申请日期 2002.10.29
申请人 CYPRESS SEMICONDUCTOR CORP. 发明人 FISCUS, TIMOTHY, E.
分类号 H03L7/081;H03L7/087;H03L7/089;(IPC1-7):H03L7/06 主分类号 H03L7/081
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