| 摘要 |
<p>A power detecting circuit and a demodulating circuit comprising it in which two transistors (FET) Q101, Q102 of substantially the same characteristics connected with a resistor element R103 as a current source at the joint of sources are employed as active elements, substantially equal bias voltages are fed to the gate and drain of the transistors Q101, Q102, a capacitor C104 set with a sufficiently high capacitance is connected between the sources of the transistors Q101, Q102 and the earth, capacitors C102, C103 set with a substantially equal and sufficiently high capacitance are connected between the drains of the transistors Q101, Q102 and the earth, a high frequency signal Rfin is fed to the gate of the transistor Q101 and the voltage difference between the drains of the transistors Q101, Q102 is detected as a detection output.</p> |
