SEMICONDUCTOR STORAGE DEVICE

摘要

An operation control circuit for use in a pseudo−SRAM apparatus in which a deep standby mode and a standby mode are set, so as to reduce the time required for returning from the deep standby mode to the standby mode. When the deep standby mode is switched to the standby mode, first and second timer circuits (12, 14) are started and each of them outputs a timer output TN of a constant cycle required for self refresh and a timing signal TR of a cycle shorter than the self refresh cycle. A counter circuit (15) counts the output TR of the second timer circuit (14) from immediately after the deep standby mode is switched to the standby mode. When the count is matched with a set value, an operation mode switching signal C is output. A selection circuit (17) composed of a multiplexer is switched/controlled by the output of the counter circuit (15) so that it selects the TR until the count value is matched with the set value and the TN afterward for output.