发明名称 |
Architecture with shared memory |
摘要 |
A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously.
|
申请公布号 |
US2003088744(A1) |
申请公布日期 |
2003.05.08 |
申请号 |
US20020117668 |
申请日期 |
2002.04.04 |
申请人 |
INFINEON TECHNOLOGIES AKTIENGESELLSCHAFT |
发明人 |
JAIN RAJ KUMAR;FRENZEL RUDI;TERSCHLUSE MARKUS;HORAK CHRISTIAN;UHLEMANN STEFAN |
分类号 |
G06F9/46;G06F12/00;G06F12/06;H01L;(IPC1-7):G06F12/00 |
主分类号 |
G06F9/46 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|