发明名称 |
Decoder an decoding method |
摘要 |
A decoder (3') inputs the probability information AMP/CRxyt obtained by dividing the channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CAxAPPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit 23 formed on a single semiconductor substrate as a large scale integrated circuit. The soft-output decoding circuit (23) generates log soft-output CIxIlambdt and/or external information 1/CAxEXt, using the first additive coefficient CR, the second additive coefficient CA and the third additive coefficient CI for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit (23). With this arrangement, it is possible to optimally select a dynamic range and a quantization slot as well as a quantization slot necessary for inner arithmetic operations if codes needs to be input with a fixed number of bits.
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申请公布号 |
US2003088823(A1) |
申请公布日期 |
2003.05.08 |
申请号 |
US20020110670 |
申请日期 |
2002.08.13 |
申请人 |
MIYAUCHI TOSHIYUKI;HATTORI MASAYUKI;YAMAMOTO KOUHEI;YOKOKAWA TAKASHI |
发明人 |
MIYAUCHI TOSHIYUKI;HATTORI MASAYUKI;YAMAMOTO KOUHEI;YOKOKAWA TAKASHI |
分类号 |
G06F11/10;H03M13/03;H03M13/23;H03M13/27;H03M13/29;H03M13/41;H03M13/45;(IPC1-7):H03M13/03 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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