Semiconductor wafer plating cell assembly

摘要

A new cell assembly for semiconductor wafer electroplating in the plated-side-up configuration utilizes a narrow passageway around the perimeter of the wafer through which solution is forced so as to provide the laminar flow needed for effective Damascene copper plating. In addition, use of a cylindrical insulating cell wall whose inside diameter matches that of the wafer area being plated avoids overplating of the wafer periphery. Anode isolation in a compartment separated via a solution transport barrier prevents introduction of particulates and holds anolyte in place during wafer changes. This cell assembly is readily amendable to automated wafer plating.